Title :
Implementation Update: Logic Mapping On SPARC- Microprocessors
Author :
Vij, Anjali ; Ratliff, Richard
Author_Institution :
Texas Instrum. Inc, Dallas, TX
Abstract :
Despite the initial proof of concept being completed almost a decade ago, the production implementations of Logic Mapping have taken significantly longer. This paper presents an update for the SPARCtrade Microprocessors, along with a discussion of some production worthiness metrics and methods applied to overcome issues on these designs. Statistical wafer level results from three current 65 nm products are shown, supplemented by analysis of some interesting packaged units.
Keywords :
automatic test pattern generation; electronic engineering computing; integrated circuit manufacture; integrated circuit packaging; logic design; microprocessor chips; SPARC microprocessors; logic mapping; production worthiness metrics; size 65 nm; statistical wafer level; Automatic test pattern generation; Availability; Inspection; Logic devices; Manufacturing; Microprocessors; Packaging; Production; Testing; Wafer scale integration;
Conference_Titel :
Test Conference, 2008. ITC 2008. IEEE International
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4244-2402-3
Electronic_ISBN :
1089-3539
DOI :
10.1109/TEST.2008.4700560
