On-chip Programmable Capture for Accurate Path Delay Test and Characterization

The increasing gap between modern chip frequencies and test clock frequencies provided by external test equipment, makes at-speed delay testing a challenge. We present a novel technique to generate a capture signal on-chip, with programmable delay, which enables faster than at-speed test. The test clock frequency can be programmed as a part of the test vector itself. Since test clock frequency can be controlled, it is no longer required to depend only on the long paths for detecting small delay defects, which provides flexibility in selecting test paths. The technique has minimal overhead in terms of area and design effort and can be easily incorporated into the current scan based delay test methods.