A parallel genetic VLSI architecture for combinatorial real-time applications-disc scheduling

Parallel genetic algorithms (PGAs) provide a means of rapidly developing a solution to a wide range of problems. In particular the parallel genetic algorithm has the potential for solving problems far faster than conventional genetic algorithm (GA). Despite these advantages real time applications are rarely discussed in the GA literature. In principle a hardware version of the PGA could cope with such real time problems. The paper proposes a new hardware based PGA using order based crossover which will be capable of optimising a new category of real time combinatorial problems. One of the few references to such a problem in the GA literature is Bennet´s Database Query Optimisation (K. Bennet et al., 1991) which finishes with the intention of developing a PGA solution with the hope of using their algorithm in real time. The hardware design presented could provide an engine for exactly this form of problem. In order to establish the benefits of the proposed hardware, disk scheduling has been identified as a common real time optimisation problem. After discussing the PGA, details of the disk scheduling problem are discussed along with conventional solutions. This is then followed by a suitable hardware design for the order based PGA and timing calculations. Simulation results are provided which contrast conventional and PGA results for disc scheduling