Shared implementation of radix-10 and radix-16 square root algorithm with limited precision primitives

We present a shared implementation of a radix-10 and radix-16 fixed-point digit-recurrence algorithm for the square root operation using limited-precision multipliers, adders, and table-lookups. We discuss the proposed algorithm, its design, and its ASIC implementation using a standard cell library. We present the cost and delay characteristics for precisions of 8 (single-precision), 16 (double-precision) for both radix-10 and radix-16 digits. The proposed scheme uses short (2-4 digit-wide) operators which leads to compact modules, reduced interconnections, reduced area and increased delay with respect to non-shared implementations.