Variation-tolerant and low-power clock network design for 3D ICs

This paper studies the random characteristics of through-silicon-via (TSV)-based 3D clock networks, taking into account both die-to-die and within-die process variations in clock buffers, interconnects, and TSVs. We investigate many design parameters which may cause clock skew variation, including the TSV RC parasitics, the TSV count, the stack die number, and the range of variations. Key insights are as follows: 1) under the circumstances of random uncorrelated TSV variation with no TSV defect, our experimental results show that the TSV variation is a new source affecting skew variability, but performs as a secondary contributor on clock skew degradation, compared with other types of random effects; 2) though several concerns exist that a 3D clock network using many TSVs may suffer from high skew variation by introducing the uncertainties of TSV electrical parasitics, our study demonstrates that a 3D clock network with multiple TSVs can decrease the random effects by using fewer buffers and shorter interconnects. The multi-TSV strategy can achieve both less power dissipation and small skew variation in 3D clock networks.