Title :
Experiments with synthesizing multiplier reduction trees
Author :
Burgess, Neil ; Lutz, David R.
Author_Institution :
ARM, Austin, TX, USA
Abstract :
This paper presents the results of synthesizing a 32-bit × 32-bit multiplier´s reduction tree at different clock frequencies. We investigate whether employing counters or compressors gives better synthesis results, and assess the impact of using radix-4 Booth coding on multiplier array delay and area.
Keywords :
counting circuits; digital arithmetic; multiplying circuits; compressor; counter; multiplier array delay; multiplier reduction tree synthesizing; radix-4 Booth coding;
Conference_Titel :
Signals, Systems and Computers (ASILOMAR), 2012 Conference Record of the Forty Sixth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
978-1-4673-5050-1
DOI :
10.1109/ACSSC.2012.6489024
