The real-time implementation of emitter identification for ESM

It is shown that no computer architecture is available providing a very high Prolog execution capability within a real-time environment. The experience gained, however, has permitted the architecture of a suitable parallel computer to be specified. The PSIDRA architecture is based on a Sequential Prolog Processor capable of 5 MLIP operation. Two Sequential Prolog processors are integrated with a Scheduler Processor to form the basic Prolog Processing Node. The PSIDRA Computer integrates these Nodes within a real-time multi-sequential operating environment. The architecture is both highly scalable and designed to meet the stringent requirements of real-time operation of programs such as CEIM and PALANTIR