Self-assembly technologies with high-precision chip alignment and fine-pitch microbump bonding for advanced die-to-wafer 3D integration

We have demonstrated surface-tension-driven chip self-assembly for 3D stacking of a large number of known good dies (KGDs) on silicon substrates in batch processing. In this work, we employed small droplets of ultra-pure water as a liquid to precisely align chips having fine-pitch indium/gold microbumps with a size/pitch of 5/10 or 10/20μm. By using the self-assembly technique, these chips were aligned in a face-down configuration and flip-chip bonded onto hydrophilic bonding areas formed on silicon substrates. The hydrophilic areas are surrounded by hydrophobic areas that have above 100° in water contact angle. The wettability contrast between the hydrophilic and hydrophobic areas was found to be a key parameter to obtain high alignment accuracy. All chips having the indium/gold microbump arrays were self-assembled with high alignment accuracy of approximately 1μm or superior accuracy, and then, successfully bonded at 200°C with thermal compression. The resulting resistance measured with the indium/gold daisy chain patterns was sufficiently low (<;20 mΩ/bump) and comparable to one obtained by a conventional mechanical alignment technique.