Time-dependent Behaviour of Full Open Defects in Interconnect Lines

Full open defects on interconnect lines cause broken wires to become floating. The voltage of a floating line depends on its topological characteristics, namely parasitic capacitances to neighbouring structures, transistor capacitances of the downstream gate(s) and trapped charge. However, in nanometer CMOS technologies gate oxide thickness is reduced below a few tens of A, resulting in the gate tunnelling leakage strongly influencing the behaviour of defective circuits with full open defects. Floating lines cannot be considered electrically isolated anymore and are subjected to transient evolutions until reaching a quiescent state, determined by the technology and the downstream gate(s). The occurrence of full opens as well as the impact of gate tunnelling leakage are expected to increase for future technologies. The transient response of full open defects on interconnect lines is analysed for nanometer technologies based on predictive technology models. A method to estimate the delay of defective circuits is proposed. Experimental evidence of this behaviour is presented for a test chip design of 0.18 mum technology.