• DocumentCode
    1734357
  • Title

    SoC design verification infrastructure

  • Author

    Gharibi, Wajeb ; Hahanov, Vladimir

  • Author_Institution
    Jazan Univ., Saudi Arabia
  • fYear
    2010
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    The testing and verification technology for system HDL models, focused to the significant improvement of the quality of design components for digital systems on chips and reduction the development time (time-to-market) by using the simulation environment, testable analysis of the logical structure HDL-program and the optimal placement of assertion engine is proposed.
  • Keywords
    integrated circuit design; integrated circuit testing; system-on-chip; SoC design verification infrastructure; digital systems; system HDL models; Controllability; Engines; Integrated circuit modeling; Observability; Registers; Software; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD), 2010 XIth International Workshop on
  • Conference_Location
    Gammath
  • Print_ISBN
    978-1-4244-6816-4
  • Type

    conf

  • DOI
    10.1109/SM2ACD.2010.5672359
  • Filename
    5672359
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1734357