Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs

Post-silicon validation is used to identify design errors in silicon. Its main limitation is real-time observability of the circuit´s internal nodes. In this paper, we introduce a novel design-for-debug architecture which automatically allocates distributed trace buffers to handle debug data acquisition requests from multiple sources located in different cores. Using resource-efficient and intelligent control placed on-chip, we show how real-time observability can be improved, thus helping bridge the gap between pre-silicon verification and post-silicon validation for SOC designs.