Analog timing recovery architectures for PRML detectors

Author

Roo, Pierte ; Spencer, Richard R. ; Hurst, Paul J.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA

Volume

1

fYear

1995

Firstpage

571

Abstract

Analog circuit implementations of decision-directed timing recovery for partial response maximum likelihood (PRML) detectors for disk drives are investigated. First, the basic equations and block diagrams are examined. The parts of the behavioral simulations of the analog system that have significant impact on choosing a topology are discussed. Our results indicate that analog implementations of decision-directed LMS timing recovery are feasible. We anticipate that these implementations will provide higher speed operation at lower power than digital implementations in a comparable technology

Keywords

CMOS analogue integrated circuits; analogue processing circuits; circuit analysis computing; continuous time systems; least mean squares methods; magnetic disc storage; maximum likelihood detection; partial response channels; phase locked loops; switched capacitor filters; timing circuits; PRML detectors; analog CMOS timing recovery circuit; analog circuit implementations; analog timing recovery architectures; basic equations; behavioral simulation; block diagrams; decision-directed LMS timing recovery; decision-directed timing recovery; disk drives; operation speed; partial response maximum likelihood; topology; Analog circuits; Clocks; Detectors; Disk drives; Equations; Finite impulse response filter; Least squares approximation; Phase detection; Phase locked loops; Semiconductor device noise; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Global Telecommunications Conference, 1995. GLOBECOM '95., IEEE

Print_ISBN

0-7803-2509-5

Type

conf

DOI

10.1109/GLOCOM.1995.501993

Filename

501993