DocumentCode
1734989
Title
CMOS technology after reaching the scale limit
Author
Iwai, Hiroshi
Author_Institution
Frontier Res. Center, Tokyo Inst. of Technol., Yokohama
fYear
2008
Firstpage
1
Lastpage
2
Abstract
Progress of CMOS LSI has been accomplished by the downsizing of MOSFETs. However, it has been expected that the downscaling will reach its limits about the gate length of 5 nm around the year of 2020. 2020 is not too far, but there is no sufficiently clear image for the world after CMOS reaches its scaling limit. This paper will discuss the picture of the CMOS technology in the world after the 2020.
Keywords
CMOS integrated circuits; MOSFET; large scale integration; CMOS large scale integrated circuits; MOSFETs; downscaling limits; CMOS integrated circuits; CMOS technology; Electronics industry; Energy consumption; Humans; Integrated circuit technology; Intelligent robots; Large scale integration; MOSFETs; Road transportation;
fLanguage
English
Publisher
ieee
Conference_Titel
Junction Technology, 2008. IWJT '08. Extended Abstracts - 2008 8th International workshop on
Conference_Location
Shanghai
Print_ISBN
978-1-4244-1737-7
Electronic_ISBN
978-1-4244-1738-4
Type
conf
DOI
10.1109/IWJT.2008.4540004
Filename
4540004
Link To Document