• DocumentCode
    1735077
  • Title

    "Plug & Test" at System Level via Testable TLM Primitives

  • Author

    Alemzadeh, Homa ; Di Carlo, Stefano ; Refan, Fatemeh ; Prinetto, Paolo ; Navabi, Zainalabedin

  • Author_Institution
    ECE Dept., Univ. of Tehran, Tehran
  • fYear
    2008
  • Firstpage
    1
  • Lastpage
    10
  • Abstract
    With the evolution of Electronic System Level (ESL) design methodologies, we are experiencing an extensive use of Transaction-Level Modeling (TLM). TLM is a high-level approach to modeling digital systems where details of the communication among modules are separated from the those of the implementation of functional units. This paper represents a first step toward the automatic insertion of testing capabilities at the transaction level by definition of testable TLM primitives. The use of testable TLM primitives should help designers to easily get testable transaction level descriptions implementing what we call a "Plug & Test" design methodology. The proposed approach is intended to work both with hardware and software implementations. In particular, in this paper we will focus on the design of a testable FIFO communication channel to show how designers are given the freedom of trading-off complexity, testability levels, and cost.
  • Keywords
    design for testability; electronic design automation; logic design; logic testing; Plug & Test design methodology; automatic insertion; design-for-testability; digital system modeling; electronic design automation; electronic system level design methodologies; functional units implementation; hardware implementation; high level approach; software implementation; testability levels; testable FIFO communication; testable TLM primitives; trading-off complexity; transaction level description; transaction-level modeling; Automatic testing; Communication channels; Costs; Design for testability; Design methodology; Digital systems; Electronic design automation and methodology; Hardware; Plugs; System testing; Design for Testability (DFT); System Level Design; System Test; Transaction Level Modeling (TLM);
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2008. ITC 2008. IEEE International
  • Conference_Location
    Santa Clara, CA
  • ISSN
    1089-3539
  • Print_ISBN
    978-1-4244-2402-3
  • Electronic_ISBN
    1089-3539
  • Type

    conf

  • DOI
    10.1109/TEST.2008.4700610
  • Filename
    4700610