Low-voltage micropower asynchronous multiplier for hearing instruments

We propose a low-voltage micropower 16×16-bit asynchronous (async) truncated multiplier design based on the Baugh-Wooley algorithm and the Wallace tree structure for an FIR filter for digital hearing instruments. We reduce the power and hardware in several ways. First, we truncate the least significant partial products in the multiplication to produce an 18-bit product that is subsequently quantized to 16-bits. Second, we employ our proposed 2-bit async adders and a 1-bit latch adder to gate the unnecessary switching. Third, we reduce the dynamic switching power by carefully selecting W/L transistor ratios in non-critical data paths. Finally, we propose the application of a simple OR gate as the completion detector circuit. We verify our design by simulations. We compare our design against reported synchronous and async designs, and show that our design has improved parameters over the reported designs.