DocumentCode :
1735208
Title :
Using Implications for Online Error Detection
Author :
Nepal, Kundan ; Alves, N. ; Dworak, Jennifer ; Bahar, R.I.
Author_Institution :
Electr. Eng. Dept., Bucknell Univ., Lewisburg, TN
fYear :
2008
Firstpage :
1
Lastpage :
10
Abstract :
In this paper, we investigate the use of logic implications for the online detection of intermittent faults and hard-to-detect manufacturing defects. We present techniques to efficiently identify the most powerful circuit implications that can be checked for violations so that the fraction of errors detected can be maximized while minimizing the additional hardware overhead. Importantly, our approach does not require re-synthesis of the targeted logic; the checker logic is added off the critical path and is run in parallel with the regular control logic. Trade-offs can be easily made between additional coverage of errors and additional area overhead. Our results show that significant error detection is possible - even with only a 10% area overhead.
Keywords :
fault diagnosis; semiconductor device manufacture; checker logic; hard-to-detect manufacturing defects; intermittent faults; logic implications; online error detection; CMOS logic circuits; CMOS process; CMOS technology; Circuit faults; Electrical fault detection; Error correction; Hardware; Power engineering and energy; Pulp manufacturing; Redundancy;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2008. ITC 2008. IEEE International
Conference_Location :
Santa Clara, CA
ISSN :
1089-3539
Print_ISBN :
978-1-4244-2402-3
Electronic_ISBN :
1089-3539
Type :
conf
DOI :
10.1109/TEST.2008.4700614
Filename :
4700614
Link To Document :
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