Title :
High-speed add-compare-select units using locally self-resetting CMOS
Author :
Jung, Gunok ; Kong, Jun Jin ; Sobelman, Gerald E. ; Parhi, Keshab K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
fDate :
6/24/1905 12:00:00 AM
Abstract :
This paper presents a new self-resetting CMOS design for an add-compare-select (ACS) unit, which is a key building block in a Viterbi decoder. Static CMOS and two-phase domino CMOS designs have also been implemented for comparison purposes. The simulation results show that, with the SRCMOS technique, the ACS units operate at a data rate of 568 Mbps in a 0.25 micron CMOS technology, as compared to 357 Mbps and 485 Mbps for static and domino CMOS implementations, respectively.
Keywords :
CMOS logic circuits; Viterbi decoding; integrated circuit design; 0.25 micron; 357 Mbit/s; 485 Mbit/s; 568 Mbit/s; Viterbi decoder; add-compare-select units; domino CMOS design; locally self-resetting CMOS design; static CMOS design; Adders; CMOS technology; Circuits; Computer architecture; Decoding; Digital communication; Memory; Pipelines; Registers; Viterbi algorithm;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1009984
