Random testing with partial circuit duplication and monitoring I/sub DDQ/

The advantage of random testing is that test application can be performed at a low cost in the BIST scheme. However, not all circuits are random pattern testable. In this paper, we present a method for improving random pattern testability of logic circuits by partial circuit duplication. The basic idea is to detect random pattern resistant faults by using the difference between the duplicated part of a circuit and the original part and detect the difference by monitoring I/sub DDQ/. Experimental results on benchmark circuits show that high fault coverage can be achieved with a very small amount of hardware overhead.