Title :
A Shared Parallel Built-In Self-Repair Scheme for Random Access Memories in SOCs
Author :
Tseng, Tsu-Wei ; Li, Jin-Fu
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Jhongli
Abstract :
Embedded memories currently constitute a significant portion of the chip area for typical system-on-chip (SOC) designs. Built-in self-repair (BISR) techniques have been widely used for enhancing the yield of embedded memories. This paper proposes a shared parallel BISR scheme for random access memories (RAMs) in SOCs. The shared parallel BISR can test and repair multiple RAMs simultaneously. A global time-multiplexed built-in redundancy analyzer (TM-BIRA) is used to allocate redundancies of the RAMs under test and repair. We also design a 1500-compatible wrapper for chip-level control of the shared parallel BISR circuits. In comparison with the dedicated parallel BISR scheme (each memory has a self-contained BISR circuit), the proposed parallel BISR scheme can achieve 20% reduction of area cost by paying additional 0.005% test and repair time for serving 5 RAMs with spare rows and spare columns.
Keywords :
built-in self test; embedded systems; logic design; logic testing; random-access storage; redundancy; system-on-chip; chip-level control; embedded memories; multiple RAM; random access memories; shared parallel BISR circuits; shared parallel built-in self-repair scheme; system-on-chip design; time-multiplexed built-in redundancy analyzer; Automatic testing; Circuit testing; Costs; Hardware; Manufacturing; Random access memory; Read-write memory; Redundancy; System-on-a-chip; Transistors;
Conference_Titel :
Test Conference, 2008. ITC 2008. IEEE International
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4244-2402-3
Electronic_ISBN :
1089-3539
DOI :
10.1109/TEST.2008.4700617
