• DocumentCode
    1735343
  • Title

    Impact of test-structure design and test methods for electromigration testing

  • Author

    Menon, Satish ; Fazekas, Josef ; Von Hagen, Jochen ; Head, Linda ; Ellenwood, Colleen H. ; Schafft, Harry A.

  • Author_Institution
    LSI Logic Corp., Milpitas, CA, USA
  • fYear
    1999
  • fDate
    6/21/1905 12:00:00 AM
  • Firstpage
    46
  • Lastpage
    53
  • Abstract
    The ultimate goal of this work is to develop design guidelines for electromigration test structures and to revise existing standard test methods for fast wafer-level and conventional package-level stress testing. These tests all involve stressing a sample of test structures and measuring their failure times to obtain sample estimates of the median-time-to-failure, t50, and the standard deviation of the loge of the failure times, or sigma(σ). Four test methods (Standard Wafer Level Electromigration Accelerated Test (SWEAT), IsoI-SWEAT, Isothermal, and ASTM) and six test structures (four SWEAT-type and two ASTM-type) were used to stress Al-1% Si metallization (1 μm and 3 μm) lines. It was observed that σ is not affected by test structure design, but is affected by the test method. σ(SWEAT) was the largest and σ(IsoI-SWEAT) was the smallest, quite understandable based on how the stress in the test methods differ. Sigma was also larger for narrower lines. The manner of terminating the test line in the ASTM-type structures did not impact lifetime, except in the narrowest lines, where the lifetime was higher for the structures with split end segments (contrary to expectations). An opening in the passivation over the heat sinks in the SWEAT-type structures did not impact lifetime. A thermal analysis showed that the usual technique of using the fractional change in resistance of the test structure to estimate the joule heating of test lines can lead to underestimates of the stress temperature. The larger the relative resistance of the heat sinks of the test structure, the greater the stress temperature of the test line will be under estimated and the lower the t50 will be. The analysis also helped explain the observed differences in the t 50 values for the different test structures
  • Keywords
    electromigration; failure analysis; integrated circuit metallisation; integrated circuit testing; thermal analysis; ASTM; AlSi; SWEAT; electromigration testing; failure time; fast wafer-level stress testing; joule heating; metallization lines; package-level stress testing; stress temperature; test-structure design; thermal analysis; Design methodology; Electromigration; Guidelines; Heat sinks; Resistance heating; Standards development; Temperature; Testing; Thermal resistance; Thermal stresses;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Integrated Reliability Workshop Final Report, 1999. IEEE International
  • Conference_Location
    Lake Tahoe, CA
  • Print_ISBN
    0-7803-5649-7
  • Type

    conf

  • DOI
    10.1109/IRWS.1999.830557
  • Filename
    830557