Title :
I/sub DDQ/ testable dynamic PLAs
Author :
Sachdev, Manoj ; Kerkhoff, Hans
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
Abstract :
Testing of bridging faults in PLAs by means of voltage testing is expensive. However, same can be done efficiently with I/sub DDQ/ testing. In this article we propose two I/sub DDQ/ testable PLA configurations. In these configurations adjacent precharge lines (and adjacent evaluation lines) are precharged (evaluated) to complementary logic levels. All likely bridging faults in these configurations are tested efficiently by the I/sub DDQ/ test technique. Such a test is independent of the function implemented in a PLA.
Keywords :
programmable logic arrays; CMOS PLA; DFT method; I/sub DDQ/ test technique; I/sub DDQ/ testable dynamic PLAs; adjacent evaluation lines; adjacent precharge lines; bridging faults; Boolean functions; CMOS logic circuits; Laboratories; Logic arrays; Logic testing; Pipelines; Power dissipation; Programmable logic arrays; Throughput; Voltage;
Conference_Titel :
IDDQ Testing, 1997. Digest of Papers., IEEE International Workshop on
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-8186-8123-3
DOI :
10.1109/IDDQ.1997.633007
