Novel diffusion-less ultra-shallow junction engineering based on millisecond annealing for sub-30 nm gate length planar bulk CMOSFET

The formation of ultra-shallow junction (USJ) less than 10 nm by using diffusion-less high-activation millisecond annealing technique has been investigated for deeply scaled planar bulk CMOS. This achievement relies on cross-sectional visualization of impurity distributions in MOSFET based on the electron beam holography technology with extremely high spatial resolution. Incorporation of cluster-ion (B₁₈H₂₂) implantation for PFETs and high-temperature millisecond-annealing, where the dedicated fabrication-process was redesigned including multiple halo implantation and thin S/D-silicidation, enables us to examine near-scaling limit bulk CMOS device performance with ultimately shallow junction. Furthermore, the parasitic resistance reduction with optimized spacing of the bottleneck at the joint of S/D-extension and deep-S/D junction was developed to overcome trade-off between the functionable minimum gate length (L_min) and on-current (I_on) of MOSFET. Those techniques that realize fully low parasitic resistance and ultimately shallow x_j extend L_min scaling to less than 30 nm for planar bulk CMOS devices.