DocumentCode
1735422
Title
High-speed pipelined A/D converter using time-shifted CDS technique
Author
Li, Jipeng ; Moon, Un-Ku
Author_Institution
Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA
Volume
1
fYear
2002
fDate
6/24/1905 12:00:00 AM
Abstract
A time-shifted correlated double sampling (CDS) technique is used to compensate for the finite opamp dc gain in the context of a pipelined analog-to-digital converter (ADC). This technique can significantly reduce the errors due to the finite opamp gain without compromising the conversion speed. This is particularly useful for the design of low-voltage and high-speed pipelined ADCs where the trade-off of opamp dc: gain and bandwidth is critical. Behavior simulation results confirm the effectiveness of this new technique.
Keywords
analogue-digital conversion; high-speed integrated circuits; low-power electronics; pipeline processing; bandwidth; conversion speed; correlated double sampling; dc gain; finite opamp dc gain; high-speed pipelined A/D converter; low voltage ADCs; time-shifted CDS technique; Analog-digital conversion; Bandwidth; CMOS technology; Computer errors; Error correction; Moon; Pipelines; Sampling methods; Signal processing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN
0-7803-7448-7
Type
conf
DOI
10.1109/ISCAS.2002.1009989
Filename
1009989
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