A pipelined A/D converter for high-speed and high-resolution application

This paper shows a novel ADC architecture, which uses the combination of multi-bit-per-stage technique for relaxing the capacitor matching requirement and the strategy employing partitioned residue gain in the first stage to achieve high speed. Matching requirements in terms of the number of bits in the first stage for high-resolution ADC are analytically discussed. Monte Carlo simulation shows that this architecture provides 100% 12-bit yield with 0.195% capacitor mismatch and 0.78% of full-scale comparator errors at 3-σ levels. The proposed analog to digital converter can be promising for high speed and high resolution applications with low power dissipation and small area.