Title :
Product reliability and maximum voltage limits from extrinsic gate oxide voltage ramp data
Author_Institution :
Cirrus Logic Inc., Fremont, CA, USA
fDate :
6/21/1905 12:00:00 AM
Abstract :
The failure rate methodology applied previously to TDDB constant voltage data is extended to VRAMP data, to obtain the failure rate for a given supply voltage and gate oxide area or conversely, the maximum supply voltage for a given failure rate. The maximum voltage limit for sub-circuits occupying a small fraction of the chip area can also be determined. The methodology relies on the effective-oxide-thickness model and the unified TDDB model, where the E-model dominates at low fields and the 1/E-model dominates at high field
Keywords :
CMOS integrated circuits; integrated circuit reliability; semiconductor device breakdown; 1/E-model; CMOS IC; E-model; TDDB constant voltage data; VRAMP data; effective-oxide-thickness model; extrinsic defect; extrinsic gate oxide voltage ramp data; failure rate; failure rate methodology; gate oxide area; high field; low fields; maximum supply voltage; maximum voltage limit; maximum voltage limits; oxide reliability; product reliability; screening; sub-circuits; supply voltage; voltage ramp; Breakdown voltage; Capacitors; Circuits; Life testing; Probability distribution; Tail; Temperature;
Conference_Titel :
Integrated Reliability Workshop Final Report, 1999. IEEE International
Conference_Location :
Lake Tahoe, CA
Print_ISBN :
0-7803-5649-7
DOI :
10.1109/IRWS.1999.830566
