Title :
IEEE 1500 Core Wrapper Optimization Techniques and Implementation
Author :
Mullane, Brendan ; Higgins, Michael ; MacNamee, Ciaran
Author_Institution :
Dept. of Electron. & Comput. Eng., Univ. of Limerick, Limerick
Abstract :
IEEE 1500 core wrappers supporting a hybrid scan mode provide for lower test times with minimal wiring and logic overheads. Wrapper logic and vector formats that are easily integrated with modern IC/FPGA design flows are demonstrated.
Keywords :
field programmable gate arrays; integrated circuit design; logic design; optimisation; IC-FPGA design flows; IEEE 1500 core wrapper optimization techniques; hybrid scan mode; logic overheads; vector formats; Automatic test pattern generation; Automatic testing; Circuit testing; Control systems; Design for testability; Field programmable gate arrays; Logic design; Logic testing; System testing; System-on-a-chip;
Conference_Titel :
Test Conference, 2008. ITC 2008. IEEE International
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4244-2402-3
Electronic_ISBN :
1089-3539
DOI :
10.1109/TEST.2008.4700629
