A High-Speed Structural Method for Testing Address Decoder Faults in Flash Memories

The low-power consumption, the high integration density and the flexibility make Flash memories popular for portable electronic devices. Unfortunately, the aggressive evolution of technologies and the particular Flash memory process induce more and more complex faults in such memories. This paper addresses the main detractor of the Flash testing time, namely the test of Address decoder Faults (AFs). The first part of the paper is devoted to an analysis of the well known 5-steps Flash test flow also called 5-steps basic sequence. Based on this analysis, the critical points of such test strategy are shown from fault coverage and test time points of view. Next, these critical points are identified and associated to a particular pattern, namely the Diagonal `0´ pattern. In the fourth part of the paper, the functional fault models (AFs) given by [1] are transposed to a structural level (St_AFs). This structural transposition opens the way to new ad-hoc test solutions. According to this transposition, a structural-based method is proposed to avoid the Diagonal `0´ pattern in a global 5-steps basic sequence. This method states on a monitoring structure that performs the detection of St_AFs. Finally, the fault coverage of our solution is evaluated and compared to the Diagonal `0´ pattern. Our solution achieves a 100% coverage rate of AFs whatever the memory size whereas the Diagonal `0´ pattern has a fault coverage that never reaches 100% and decreases with the memory size.