Design and implementation of a self-calibrating floating-point analog-to-digital converter

Floating point analog-to-digital converters (FP-ADC) are characterized by a high relative precision, but, in some applications, their absolute precision had to be traded off for speed. This paper presents the architecture, design and implementation of a self-calibrating differential predictive floating point analog-to-digital converter which is characterized by high conversion rates while its precision is kept at high values by additional hardware that periodically performs calibration cycles. Experimental measurements were carried out to test this FP-ADC and the acquired results are presented, as well.