A Novel Pattern Generation Framework for Inducing Maximum Crosstalk Effects on Delay-Sensitive Paths

The limitations of pattern generation tools are beginning to surface as parasitic coupling capacitance in high speed interconnects only worsens as the industry approaches sub-50 nm technologies. This can create a gap between the delay experienced on critical and long paths during test and the delay of the same paths in the field. In this paper, we propose a novel structural test pattern generation procedure that magnifies parasitic crosstalk effects on delay-sensitive paths by inducing switching on nearby nets which have been identified using the parasitic information of the layout. This will ensure timing closure on the targeted path is still met while also minimizing escape ratio and improving in the field reliability. Results of the proposed layout-aware approach demonstrate the ability of the proposed framework to significantly increase crosstalk around the targeted delay-sensitive paths.