A 2-mW Power Consumption Low Noise Amplifier in PD SOI CMOS Technology for 2.4 GHz Applications

Author

El Kaamouchi, M. ; Moussa, M. Si ; Raskin, J.-P. ; Vanhoenacker-Janvier, D.

Author_Institution

Microwave Lab., Univ. Catholique de Louvain, Louvain-la-Neuve

fYear

2007

Firstpage

253

Lastpage

256

Abstract

This paper reviews and analyzes a fully integrated low-noise amplifier (LNA) for low-power and narrow-band applications using a cascode inductive source degeneration topology, with a body contacted transistor in 130 nm partially depleted CMOS SOI technology. Thanks to the SOI technology, the LNA shows only 2 mW power consumption when power gain of 10 dB and a noise figure of 3.1 dB at 2.4 GHz are measured for 1.2 V supply voltage

Keywords

CMOS analogue integrated circuits; UHF amplifiers; low noise amplifiers; low-power electronics; silicon-on-insulator; 1.2 V; 10 dB; 130 nm; 2 mW; 2.4 GHz; 3.1 dB; PD SOI CMOS technology; cascode inductive source degeneration topology; low noise amplifier; noise figure; power consumption; transistor; CMOS technology; Energy consumption; Gain measurement; Low-noise amplifiers; Narrowband; Noise figure; Noise measurement; Power measurement; Topology; Voltage; CMOS; Low Noise Amplifier; PD SOI; cascode; inductive source degeneration; narrow-band;

fLanguage

English

Publisher

ieee

Conference_Titel

Silicon Monolithic Integrated Circuits in RF Systems, 2007 Topical Meeting on

Conference_Location

Long Beach, CA

Print_ISBN

0-7803-9764-9

Electronic_ISBN

0-7803-9765-7

Type

conf

DOI

10.1109/SMIC.2007.322806

Filename

4117373