Title :
The Limits of Compression
Author_Institution :
Synopsys Inc., Boulder, CO
Abstract :
The use of scan-based compression techniques is becoming mandatory on current designs. While high compression is desired to hold the test costs within limits, it is important to understand what bounds exist that governs the ultimate compression. My position is simply that the network on chip determines the maximum compression not the engineer or for that matter not the test EDA salesperson.
Keywords :
logic testing; network-on-chip; network on chip; scan-based compression technique; Automatic test pattern generation; Compaction; Costs; Electronic design automation and methodology; Encoding; Entropy; Network-on-a-chip; Sequential analysis; Testing; Upper bound; Scan compression; combinational / sequential compression; compression bounds; design for compression; entropy;
Conference_Titel :
Test Conference, 2008. ITC 2008. IEEE International
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4244-2402-3
Electronic_ISBN :
1089-3539
DOI :
10.1109/TEST.2008.4700670
