Matching considerations in I/Q A/D converter pairs

Data characterizing the relationship between image reject ratio (IRR) and process mismatches in pipeline analog-to-digital converter (ADC) pairs is presented. The general high-level simulation model consists of two pipeline ADCs in parallel placed in an environment that resembles the I- and Q-channels of an RF receiver. Inserting normally distributed mismatches into the components of each ADC provides data that monitors any correlation between these mismatches and the IRR. This correlation was observed under a variety of conditions and calibration techniques. In particular, simulation evidence suggests that digital calibration techniques aimed at assisting linearity actually reduce the efficacy of I- and Q-channel image rejection.