A CMOS phase-locked loop with an auto-calibrated VCO

A new phase-locked loop (PLL) architecture is presented. This PLL has a mechanism that continuously autocalibrates its operating frequency with respect to a reference clock frequency. One advantage of using auto-calibration is that a wide operating frequency range can be covered, while maintaining a relatively low VCO conversion gain, K_VCO. The direct impact of a low conversion gain VCO is a low phase noise sensitivity of the whole system.