• DocumentCode
    1736887
  • Title

    Overview of IEEE P1450.6.2 Standard; Creating CTL Model For Memory Test and Repair

  • Author

    IEEE P1450.6.2 Working Group

  • fYear
    2008
  • Firstpage
    1
  • Lastpage
    1
  • Abstract
    A new standard, P1450.6.2 is being developed to provide the syntax and semantics to support the memory test and repair requirements. The poster provides an introduction to the proposed standard. The syntax of the main CTL blocks is presented to demonstrate the effectiveness in addressing complicated memory testing requirements. An elaborate example is used to highlight the advantages of the memory CTL model.
  • Keywords
    IEEE standards; integrated circuit testing; CTL model; IEEE P1450.6.2 standard; core test language; memory test and repair; Automatic testing; Pins; Random access memory; Read-write memory; Signal design; Signal processing; Standards development; Timing; Topology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2008. ITC 2008. IEEE International
  • Conference_Location
    Santa Clara, CA
  • ISSN
    1089-3539
  • Print_ISBN
    978-1-4244-2402-3
  • Electronic_ISBN
    1089-3539
  • Type

    conf

  • DOI
    10.1109/TEST.2008.4700680
  • Filename
    4700680
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1736887