Author :
Bahl, Swapnil ; Sarkar, Rajiv ; Garg, Akhil
Author_Institution :
STMicroelectronics Pvt. Ltd., Noida
Abstract :
The power consumed during test mode is higher than the functional mode and becomes significantly higher for low power devices. The increased heat can result in chip burnouts and reliability issues due to electro-migration. This poster presents the reasons for higher power consumption, its consequences, and various solutions, both at hardware and software level, for reducing the overall test mode power. It also highlights the benefits, costs and practicability by applying it on few ST SoCs.
Keywords :
electromigration; integrated circuit testing; reliability; system-on-chip; SoC; chip burnouts; electromigration; low power devices; reliability; test mode power; Automatic testing; Clocks; Costs; Energy consumption; Filling; Hardware; Logic testing; Signal design; Software testing; Vehicle dynamics;
Conference_Titel :
Test Conference, 2008. ITC 2008. IEEE International
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4244-2402-3
Electronic_ISBN :
1089-3539
DOI :
10.1109/TEST.2008.4700682
