• DocumentCode
    1737114
  • Title

    Hardware Overhead Reduction for Memory BIST

  • Author

    Arai, Masayuki ; Iwasaki, Kazuhiko ; Nakao, Michinobu ; Suzuki, Iwao

  • Author_Institution
    Tokyo Metropolitan Univ., Tokyo
  • fYear
    2008
  • Firstpage
    1
  • Lastpage
    1
  • Abstract
    We propose encoder-based comparator architecture to reduce hardware overhead of MBIST. Experimental results show the proposed architecture drastically reduce hardware overhead while maintaining the adaptability to the repair analysis.
  • Keywords
    SRAM chips; built-in self test; comparators (circuits); integrated circuit testing; logic testing; SRAM; built-in self-test; encoder-based comparator architecture; hardware overhead reduction; memory BIST; Built-in self-test; Circuit faults; Circuit simulation; Fault location; Hardware; Logic; Random access memory; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2008. ITC 2008. IEEE International
  • Conference_Location
    Santa Clara, CA
  • ISSN
    1089-3539
  • Print_ISBN
    978-1-4244-2402-3
  • Electronic_ISBN
    1089-3539
  • Type

    conf

  • DOI
    10.1109/TEST.2008.4700690
  • Filename
    4700690
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1737114