A Low-Cost Programmable Memory BIST Design for Multiple Memory Instances

In this work, we propose a hardware-sharing P-MBIST design to test multiple memory instances with different types in one BIST design. By sharing a common address generator and controller, the area overhead is significantly reduced in comparison to existing works. A high-speed address generator with column-scan feature is also proposed for at-speed/full-speed tests. The proposed P-MBIST design can be automatically generated according to a user-defined configuration file. A priority-based verification process for the soft IP is also presented in this work.