Efficient computation of logic circuits reliability based on Probabilistic Transfer Matrix

The development of fault tolerance techniques to enhance systems dependability is becoming an unavoidable task as IC industry enters in the nanoscale era. However, before consider the fault tolerant design, an accurate method of reliability evaluation is necessary. The knowledge of the natural error masking capabilities of a given circuit will be essential to handle design tradeoffs in the conception stage. This paper is intended to deal with improvements in the reliability computation of logic circuits using the probabilistic transfer matrix (PTM) approach. We propose an algorithm that reduces memory requirements and can improve run-time performances in the most significant stage of the PTM algorithm, keeping the same accurate reliability analysis.