• DocumentCode
    173793
  • Title

    On the design of efficient modulo 2n+1 multiply-add-add units

  • Author

    Efstathiou, C. ; Tsoumanis, K. ; Pekmestzi, K. ; Voyiatzis, Ioannis

  • Author_Institution
    Technol. Inst. of Athens, Athens, Greece
  • fYear
    2014
  • fDate
    6-8 May 2014
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    In this work efficient modulo 2n+1 fused multiply-add-add units for weighted and diminished-1 operands are proposed. The proposed architectures can be applied in systems in which fused multiply-add-add units accelerate the execution of the targeting algorithms. Long integer arithmetic would also show considerable gains by using multiply-add-add units. Also, implementation results for the proposed units are given and compared to the performance of existing designs.
  • Keywords
    digital arithmetic; logic design; multiplying circuits; diminished-1 operand; efficient modulo 2n+1 fused multiply-add-add unit design; integer arithmetic; weighted operand; Adders; Algorithm design and analysis; Complexity theory; Computer architecture; Digital signal processing; Signal processing algorithms; Vectors; RNS; diminished-1; fused multiply-add-add units; modulo 2n+1; residue number system; weighted;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design & Technology of Integrated Systems In Nanoscale Era (DTIS), 2014 9th IEEE International Conference On
  • Conference_Location
    Santorini
  • Type

    conf

  • DOI
    10.1109/DTIS.2014.6850645
  • Filename
    6850645
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=173793