DocumentCode :
173795
Title :
Low overhead output response compaction in RAS architectures
Author :
Voyiatzis, Ioannis ; Efstathiou, C. ; Sgouropoulou, K.
Author_Institution :
Dept. of Inf., Technol. Educ. Inst. of Athens, Athens, Greece
fYear :
2014
fDate :
6-8 May 2014
Firstpage :
1
Lastpage :
3
Abstract :
Scan design causes high switching activity during testing which results in high power dissipation. Therefore, an alternative scheme, termed Random Access Scan (RAS, initially proposed by Ando during the early 80´s) has regained interest due to its low power consumption. RAS-based schemes result in considerable reduction in power dissipation; furthermore they have been shown to compare favorably to scan based schemes with respect to hardware overhead. Response compaction in RAS architectures is typically performed using Multiple-Input Shift Register (MISR) structures. In this work we propose a response compaction scheme for RAS architectures which, compared to the utilization of MISR structures, results in lower hardware overhead and lower time required to capture the responses.
Keywords :
VLSI; boundary scan testing; low-power electronics; shift registers; MISR; RAS architectures; VLSI; hardware overhead; low power consumption; multiple input shift register; power dissipation reduction; random access scan; response compaction; scan design; Benchmark testing; Compaction; Computer architecture; Hardware; Logic gates; Radiation detectors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design & Technology of Integrated Systems In Nanoscale Era (DTIS), 2014 9th IEEE International Conference On
Conference_Location :
Santorini
Type :
conf
DOI :
10.1109/DTIS.2014.6850646
Filename :
6850646
Link To Document :
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