• DocumentCode
    173856
  • Title

    Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization

  • Author

    Becker, B. ; Drechsler, Rolf ; Eggersgluss, Stephan ; Sauer, Matthias

  • Author_Institution
    Dept. of Comput. Sci. (IIF), Univ. of Freiburg, Freiburg, Germany
  • fYear
    2014
  • fDate
    6-8 May 2014
  • Firstpage
    1
  • Lastpage
    10
  • Abstract
    It is well-known that in principle automatic test pattern generation (ATPG) can be solved by transforming the circuit and the fault considered into a Boolean satisfiability (SAT) instance and then calling a so-called SAT solver to compute a test. More recently, the potential of SAT-based ATPG has been significantly extended. In this paper, we first provide introductory knowledge on SAT-based ATPG and then report on latest developments enabling applications far beyond classical ATPG.
  • Keywords
    automatic test pattern generation; computability; logic circuits; logic testing; optimisation; Boolean SAT instance; Boolean satisfiability instance; SAT solver; SAT-based ATPG; nonstandard fault model; principle ATPG; principle automatic test pattern generation; Automatic test pattern generation; Circuit faults; Computational modeling; Delays; Integrated circuit modeling; Logic gates; Optimization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design & Technology of Integrated Systems In Nanoscale Era (DTIS), 2014 9th IEEE International Conference On
  • Conference_Location
    Santorini
  • Type

    conf

  • DOI
    10.1109/DTIS.2014.6850674
  • Filename
    6850674