DocumentCode
1738935
Title
Design and performance of Maestro cluster network
Author
Yamagiwa, Shinichi ; Fukuda, Munehiro ; Wada, Koichi
Author_Institution
Inst. of Inf. Sci. & Electron., Tsukuba Univ., Ibaraki, Japan
fYear
2000
fDate
2000
Firstpage
35
Lastpage
44
Abstract
Most clusters so far have used WAN or LAN-based network products for communication due to their market availability. However they do not always match communication patterns in clusters, thus incurring extra overhead. Based on our investigation for such overhead, we have optimized cluster communication at link layer. Partitioning each message in 16-byte packets, our optimization uses two techniques: (1) transferring in burst as many packets as the receiving buffer accepts at once, and (2) having each hardware component pass one packet to another in a pipelined manner. We have realized those two techniques in a link control hardware chip, referred to as MLC(Maestro Link Controller), and have constructed the Maestro cluster network using MLCs. This paper describes the feature of the Maestro cluster network and demonstrates the efficiency of our optimization techniques through performance experiments over this network
Keywords
LAN interconnection; performance evaluation; wide area networks; workstation clusters; LAN-based network; Maestro Link Controller; Maestro cluster network; WAN; cluster communication; communication patterns; link control hardware chip; performance evaluation; performance experiments; Communication system control; Consumer electronics; Delay; Hardware; Kernel; Pattern matching; Protocols; Software performance; Throughput; Wide area networks;
fLanguage
English
Publisher
ieee
Conference_Titel
Cluster Computing, 2000. Proceedings. IEEE International Conference on
Conference_Location
Chemnitz
Print_ISBN
0-7695-0896-0
Type
conf
DOI
10.1109/CLUSTR.2000.888990
Filename
888990
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