Analysis of the migration of the defects induced by high-dose ion implantation of arsenic in silicon

A frequent failure mechanism in I.C.´s CMOS polysilicon gate technology is the punch-through of NMOS transistor junction. The high doped drain-source N⁺ zone is obtained by high dose arsenic ion implantation. During the ion implantation an important amount of damage is induced in the silicon substrate and in the following thermal processes there appears a migration of the dislocations. We suppose that the migrating damage is in charge of the failure mechanism. The purpose of this paper is to identify the zone with maximum damage and to prove the migration of the defects during the thermal annealing. Finally is advanced a simple empirical model that allows predicting the final position/dimension of the silicon substrate damage zone