A novel approach for constructing reversible fault tolerant n-bit binary comparator

Nowadays fault tolerant reversible logic is becoming popular and have widely used in reducing power consumption of digital logic design. Reversible logic is used to optimize power by recovering bit loss from its unique input-output mapping. In this paper, for the first time we designed a novel approach for constructing fault tolerant reversible n-bit binary comparator. An algorithm has been presented for constructing the novel fault tolerant reversible comparator circuit. We designed two new fault tolerant reversible gates namely AG, and FTSEG to optimize the number of gates, garbage outputs, quantum cost, constant inputs and delay of the circuit. Two lemmas are also presented to prove the fault tolerance or parity preserving property for the proposed two fault tolerant reversible gates AG and FTSEG respectively. The simulation results of the proposed fault tolerant reversible design show that the circuit works correctly.