Title :
Delay-bound guarantee in combined input-output buffered switches
Author :
Chao, H. Jonathan ; Chen, Li-Sheng
Author_Institution :
Dept. of Electr. Eng., Polytech. Univ. of Brooklyn, NY, USA
Abstract :
CIOB (combined input-output buffered) switches with a moderate speedup have been widely considered as the most feasible solution for large-capacity switches. In this paper, we adopt the hierarchical link sharing (HLS) algorithm in non-blocking CIOB switches to guarantee delay bound that is independent of the switch size. We also propose a feasible architecture to implement the HLS algorithm in the switch, which can accommodate the packet carried over a 10 Gbit/s line without a speedup requirement. Furthermore, we design a new serial comparator to find minimum time-stamp values
Keywords :
buffer storage; delays; packet switching; scheduling; 10 Gbit/s; CIOB switches; HLS algorithm; combined input-output buffered switches; delay-bound guarantee; hierarchical link sharing algorithm; large-capacity switches; minimum time-stamp values; nonblocking switch; packet switch; serial comparator; Bandwidth; Chaos; Delay; Fabrics; High level synthesis; Packet switching; Scheduling algorithm; Switches; Throughput; Traffic control;
Conference_Titel :
Global Telecommunications Conference, 2000. GLOBECOM '00. IEEE
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-6451-1
DOI :
10.1109/GLOCOM.2000.892057
