DocumentCode
1739872
Title
DFT and BIST techniques for the future
Author
Wang, Hsin-Po ; Turino, Jon
Author_Institution
SynTest Technols. Inc., Taiwan
fYear
2000
fDate
2000
Firstpage
6
Lastpage
7
Abstract
In this age of increasingly complex multi-million gate system-on-chip (SoC) device designs, coupled with multinational design and fabrication strategies to speed time to market for new products, new strategies are needed for insuring that new integrated circuit (IC) designs can be tested to very high levels of quality with very economical production test times
Keywords
built-in self test; design for testability; integrated circuit economics; logic testing; production testing; BIST; DFT; IC design; economics; integrated circuit design; multimillion gate system-on-chip; multinational design; quality; time to market; Built-in self-test; Circuit testing; Coupling circuits; Design for testability; Fabrication; High speed integrated circuits; Integrated circuit testing; System testing; System-on-a-chip; Very high speed integrated circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian
Conference_Location
Taipei
ISSN
1081-7735
Print_ISBN
0-7695-0887-1
Type
conf
DOI
10.1109/ATS.2000.893591
Filename
893591
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