DocumentCode :
1739877
Title :
High-speed generation of LFSR signatures
Author :
Shieh, Ming-Der ; Lo, Hsin-Fu ; Sheu, Ming-hwa
Author_Institution :
Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Taiwan
fYear :
2000
fDate :
2000
Firstpage :
222
Lastpage :
227
Abstract :
We investigate techniques for speeding up the compaction simulation of a single-input signature register based on its equivalent multiple-input implementation. Our approach is to systematically decompose the original input sequence into a set of subsequences based on the theory of finite field. High-speed signature computations can then be achieved by inputting those subsequences at the same time and employing the lookahead technique for those subsequences to speed up compaction. Both the internal-XOR and external-XOR LFSRs are implemented to demonstrate the flexibility of our development. Compared with the existing methods that were mainly developed for software programming, our results are suitable for both software and hardware implementation and have the potential of reducing the memory requirement of off-line determination of signatures
Keywords :
automatic test pattern generation; binary sequences; built-in self test; integrated circuit testing; logic testing; performance evaluation; BIST; LFSR signatures; compaction simulation; equivalent multiple-input implementation; external-XOR LFSR; finite field theory; high-speed generation; high-speed signature computations; internal-XOR LFSR; linear feedback shift register; lookahead technique; single-input signature register; subsequences; Automatic testing; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Compaction; Computational modeling; Galois fields; Hardware; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian
Conference_Location :
Taipei
ISSN :
1081-7735
Print_ISBN :
0-7695-0887-1
Type :
conf
DOI :
10.1109/ATS.2000.893629
Filename :
893629
Link To Document :
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