Title :
Strong self-testability for data paths high-level synthesis
Author :
Li, Xiaowei ; Masuzawa, Toshimitsu ; Fujiwara, Hideo
Author_Institution :
Dept. of Comput. Sci., Beijing Univ., China
Abstract :
In this paper, we introduce strong self-testability for data paths at register transfer level (RTL). A high-level synthesis scheme is proposed for producing such strongly self-testable data paths. This is achieved by incorporating testability constraints during processes of register assignment and interconnection assignment. This method is based on the use of test resources reusability to improve the self-testability of data path. Experimental results are presented to demonstrate the effectiveness of the proposed approach
Keywords :
data flow graphs; design for testability; high level synthesis; data paths; high-level synthesis; interconnection assignment; register assignment; register transfer level; self-testability; test resources reusability; testability constraints; Automatic testing; Built-in self-test; Circuit synthesis; Circuit testing; Computer science; Concurrent computing; High level synthesis; Logic testing; Semiconductor device testing; Test pattern generators;
Conference_Titel :
Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian
Conference_Location :
Taipei
Print_ISBN :
0-7695-0887-1
DOI :
10.1109/ATS.2000.893630
