An integrated low-noise CMOS PLL frequency synthesis

Author

Zhang, Chunhui ; Li, Yongming ; Chen, Hongyi ; Zhang, Hao

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing, China

Volume

1

fYear

2000

fDate

2000

Firstpage

635

Abstract

A fully monolithic prototype frequency synthesis based on a phase-locked loop (PLL) is described. To overcome the affections of noise, all the circuits of the synthesizer use a differential architecture and the digital parts designed by state logic. The voltage control oscillator (VCO) utilizing a modified ECL scheme provides low noise and operates over a wide range of power supply voltage. The experimental VCO has a frequency range from 700 MHz to 1.05 GHz. The test chip was designed in a standard 0.6 μm n-well CMOS technology, consuming 95 mW at maxim frequency from a 5 V supply

Keywords

CMOS logic circuits; emitter-coupled logic; frequency synthesizers; phase locked loops; voltage-controlled oscillators; 0.6 mum; 5 V; 700 MHz to 1.05 GHz; 95 mW; UHF; VCO; differential architecture; frequency range; integrated low-noise CMOS PLL; low noise; modified ECL scheme; monolithic prototype frequency synthesis; n-well CMOS technology; noise; phase-locked loop; power supply voltage; state logic; test chip; voltage control oscillator; CMOS logic circuits; CMOS technology; Frequency synthesizers; Integrated circuit synthesis; Logic circuits; Logic design; Phase locked loops; Prototypes; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Proceedings, 2000. WCCC-ICSP 2000. 5th International Conference on

Conference_Location

Beijing

Print_ISBN

0-7803-5747-7

Type

conf

DOI

10.1109/ICOSP.2000.894568

Filename

894568