Title :
Asynchronous Gb/s signaling for digital communication
Author_Institution :
Cisco Syst., San Jose, CA, USA
Abstract :
This presentation covers the measurement and simulation techniques for the analysis of 2.5-4.8 Gb/s systems. Comparison of measurements to theoretical calculations for transmission lines in a laminate material system are also shown. This includes the effects of vias, skin loss and dielectric loss. An overview of the current serializer-deserializer (SerDes) technology is given, with emphasis on equalization techniques and benefits. Finally, a demonstration of an existing backplane system is compared to the simulation results
Keywords :
CMOS integrated circuits; data communication equipment; digital communication; equalisers; high-frequency transmission lines; integrated circuit interconnections; integrated circuit packaging; 2.5 to 4.8 Gbit/s; CMOS; SerDes technology; asynchronous signaling; backplane system; dielectric loss; digital communication; equalization techniques; laminate material system; measurement techniques; serializer-deserializer technology; simulation; simulation techniques; skin loss; transmission lines; vias; Analytical models; Backplanes; Dielectric losses; Dielectric materials; Dielectric measurements; Digital communication; Laminates; Skin; Transmission line measurements; Transmission line theory;
Conference_Titel :
Electrical Performance of Electronic Packaging, 2000, IEEE Conference on.
Conference_Location :
Scottsdale, AZ
Print_ISBN :
0-7803-6450-3
DOI :
10.1109/EPEP.2000.895482
